The King of Video Protocols
DisplayPort (DP) was created by the VESA to succeed all previous video standards. It has all the features of earlier protocols and more.
Some of these include: packetized data transport fast data rates (and thus higher resolutions) with up to 16 bits per color component embedded audio a high-speed auxiliary communications channel multiple video channels over the same cable
All DisplayPort specifications after version 1.1a are only available for paying members of VESA, or for a pretty high fee.
Still, a lot of information can be gotten from the 1.1a spec. You can download it here after filling in a bit of personal information
DisplayPort connector has 20 pins.
11 of those are functionally important:
- 8 pins are used for 4 differential pairs that are used to transport data.
- 2 pins are used for 1 differential pair that transports auxiliary data.
- 1 pin is used for hot plug detect. This is used to inform the source that there is a sink on the other side of the cable.
The remaining pins are used as follows:
- 4 pins are used for ground.
- 2 pins are CONFIG pins that are always connected to ground in practice.
- 1 pin is used as a power supply pin. See The DisplayPort Pin 20 Problem.
- 1 pin is used for return of power.
Contrary to VGA, which is a pure analog signal, and DVI/HDMI, which has uses a separate clock signal, DP has self-clocked data lines with low-level differential signalling (LVDS).
Now what does that mean in practice?
With DVI/HDMI, there are a number of paired wires for data over which data can be transferred at various clock speeds. A separate wire carries the actual pixel clock.
In DP, there are only a fixed number of allowed clock speeds. Before transmitting actual data, the source and sink first negotiate an appropriate clock speed during the so-called link training procedure. Once both sides agree, the source starts sending data at this fixed clock speed. There is no need to have a separate clock.
(Show picture of data bits flowing over DP)
- Source creates 8 wires with clean zeros and ones.
- Transmission medium garbles the data into something impossible to decode just like that.
- External influences also inside some common mode noise.
- 8 signals coming in with noise, in differential pairs. (Show some common mode noise on them.)
- 4 signals coming in, completely garbled, but without common mode noise.
- 4 signals with a data-eye after CTL and equalization (Show some skew between the different pairs.)
- Clock being recovered from the transition on pair 0
- Sample clocks are delayed versions of clock to account for skew
- Serial bitstream recovered from each pair.
- 10-bit words are extracted from the bit stream based on special synchronization code words
- 10-bit words are converted into 8-bit data words and 1-bit k-code.
- Black box: convert the 4 parallel streams of data into pixels, audio, and other stuff.
Even though a particular clock speed has negotiated, that doesn't mean that the reciever can simply program a clock generator on its side and just hope that all bits on the wire can simply be sampled and converted in parallel data: there will always some minute difference between a source and sink clock generator.
Instead, the agreed upon clock value will be used to prepare the logic in the receiver for a certain data rate at which bits and pixels will arrive.
There will still be a PLL that will observe the transistions from 0 to 1 and back on the first data line, and generate a clock that is fully synchronous with the source from those transitions. Similar DVI/HDMI, the data for DP has been encoded such that there will always be sufficient transitions from 0 to 1 and back, even if the actual pixel data is constant.
Once the clock has been successfully recovered, there's yet another step where a delay is added to the clock to ensure that the data is sampled right in the middle of the data-eye of the signal: the point in time in between signal transitions where the it most stable. This reduces the chance of sample errors.
- Connector Pin Assigment: DisplayPort Version 1.1a, 22.214.171.124, page 195.
- VESA DisplayPort Presentation